Thanks Allan.
I sent it through the Software Forum. I get the answer that my question belongs to the Chipset Forum..
I'll appreciate your help..
I think that power-up and PCIe link questions can be answered better by Chipses\Hardware fellows..
A summarized question is attached below.
Thank you again,
Lior.
***
Using COM Express™, Intel® Core™ i7 Celeron processor, Intel® 5 Series HM55 chipset.
Also, An Altera™ Startix IV FPGA. is placed on the carrier.
Facing a PCIe "no communication" problem when Windows OS starts.
Can anybody draw guidelines for the Power-Up Sequence and/or using the PWR_OK signal and the SYS_RESET# signal?
What is the typical timing for the SYS_RESET#? What is the maximum period of time that a delay before PWR_OK can be set safely?
What should be the length of the pulse of SYS_RESET#?
Thank you very much in advance,
Lior Mor.
http://www.congatec.com/fileadmin/user_upload/Documents/Manual/BM57_BS57_BE57m12.pdf